The invention relates to memory devices, and more particularly to a phase change memory (PCM) cell structure and a method for fabricating the same.
Phase change memory devices are non-volatile, highly readable, highly programmable, and require a relatively lower driving voltage/current. Current trends in phase change memory development are to increase cell density and reduce current density thereof.
Phase change material in a phase change memory devices have at least two solid phases, a crystalline state and an amorphous state. Transformation between these two phases can be achieved by changing the temperature of the phase change material. The phase change material exhibits different electrical characteristics depending on its state. For example, in its amorphous state the material exhibits a higher resistivity than in the crystalline state. Such phase change material may switch between numerous electrically detectable conditions of varying resistivities within a nanosecond time scale with the input of pico joules of energy. Chalcogenide material is a popular and widely used phase change material in modern phase change memory technology.
Since phase change material permits reversible phase transformation, memory bit status can be distinguished by determining the phase of phase change material in the memory bit.
FIG. 1 is a schematic diagram of a cross section of a conventional phase change memory cell structure, in which the phase change memory cell structure includes an isolation structure 13 is located at a predetermined region of a semiconductor substrate 11 to thereby define an active region. A source region 17s and a drain region 17d are also disposed apart in the active region. A gate 15, functioning as a word line, is disposed across the active region between the source region 17s and the drain region 17d. The gate 15, the source region 17s and the drain region 17d form a transistor. The semiconductor substrate 11 having the transistor thereon is covered with an insulating layer 19. An interconnection line 21 is disposed over the first insulating layer 19. The interconnection line 21 is electrically connected to the drain region 17d through a contact hole penetrating the first insulating layer 19. Another insulating layer 23 covers the interconnection line 21. A heating plug 25 is disposed in the insulating layers 19 and 23, electrically connecting the source region 17s. A patterned phase change material layer 27 and a top electrode 29 are sequentially stacked over the insulating layer 23, wherein a bottom surface of the phase change material layer pattern 27 is in contact with the heating plug 25. Another insulating layer 31 is disposed on the insulating layer 23. A bit line 33 is disposed on the insulating layer 31 and is in contact with the top electrode 29.
In a write mode, the transistor is turned on and a large current flows through the heating plug 25, thus heating up an interface between the phase change material layer pattern 27 and the heating plug 25, thereby transforming a portion 27a of the phase change material layer 27 into either the amorphous state or the crystalline state depending on the length of time and amount of current that flows through the heating plug 25.
One problem is found with conventional phase change devices, is the relatively large amount of current required to successfully change the state of the phase change material during a write operation. One solution to increasing current density is to reduce a diameter D of the heating plug 25. An aspect ratio of an opening (not shown) for disposing the heating plug 25 formed through the insulating layers 23 and 19 increases when the diameter D of the heating plug 25 is reduced. Since the heating plug 25 is typically formed by processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), heating plug 25 may be thus form with undesired structures such as seams or voids therein as long as increase of the aspect ratio of the opening for disposing thereof and may thereby degrade reliability thereof. Therefore, reliability of a phase change material memory cell structure with such heating plugs is affected and size reduction thereof is problematic.